1. Field of the Invention
The present invention relates to a regulated power supply circuit and, more specifically, to a regulated power supply circuit which prevents lowering of the regulation range even when a load current increases as well as suppresses lowering of the output voltage which is contrary to a conventional regulator outputting a regulated electric power of which regulation range is normally narrowed and decreases correspondingly depending on an increase of the load current.
2. Background Art
As an example of conventional CMOS type regulated power supply circuits formed in an IC, a power source voltage regulation circuit (regulator) as illustrated in FIG. 3 is exemplified which is constituted by a differential amplifier circuit 10 and a current output circuit (a current booster circuit) 11 making use of a bipolar transistor at the output stage thereof.
In this circuit, numeral 12 is an output terminal at which a regulated voltage is provided and to which a load L is connected. Numeral 13 is a constant voltage power source generating a reference voltage Vr which is applied to one input of the differential amplifier circuit 10. The differential amplifier circuit 10 includes inside thereof a differential amplifier 10a and a constant current source 10b having a current value of I. Further, at the output side of the current booster circuit 11 a series circuit of resistors R1 and R2 is inserted between the output terminal 12 and the ground GND in parallel with the load L.
Herein, the differential amplifier 10a includes a pair of PNP type bipolar transistors Q1 and Q2 which perform a differential operation and NPN type bipolar transistors Q3 and Q4 in a current mirror connection which are provided between collectors of the respective bipolar transistors Q1 and Q2 and the ground GND as an active load. To the base of the transistor Q1 the reference voltage Vr is applied, the both emitters of the bipolar transistors Q1 and Q2 are connected in common and are connected via a constant current source 10b to a predetermined power source line VDD which is roughly regulated by such as a capacitor.
The base of the transistor Q2 is connected to a junction point N of the resistors R1 and R2 and receives a fed back voltage from the output side of the current booster circuit 11. Further, the output derived from the collector side of the transistor Q4 is applied to the base of an NPN type bipolar transistor Q5 at the input stage in the current booster circuit 11. The transistor Q5 is one for driving a current output stage transistor Q6, and of which emitter is grounded and of which collector is connected to the base of the PNP type bipolar transistor Q6 at the current output stage as well as to a power source line Vcc which is higher than the predetermined power source line VDD through a resistor R3. The transistor Q5 drives the transistor Q6 in response to an output current derived from the collector side of the transistor Q4. Still further, the emitter of the transistor Q6 is connected to the output terminal 12.
In this circuit, the voltage at a terminal (the junction point N) of the resistor R2 is fed back to the base of the transistor Q2 in the differential amplifier circuit 10, the differential amplifier circuit 10 operates so as to equalize the terminal voltage appearing at the resistor R2 with the reference voltage Vr and to generate a regulated onstant voltage Vo at the output terminal 12.
The constant voltage Vo is expressed as follows; EQU Vo=(r1+r2).multidot.Vr/r2
wherein r1 is a resistance of the resistor R1 and r2 is a resistance of the resistor R2.
FIG. 4 shows a load current Io-output voltage Vo characteristic of such a regulated power supply circuit and, as illustrated by the dotted line, the output voltage Vo decreases depending on increase of the load current. In contrast to an ideal regulation as illustrated by the solid line, the output voltage Vo decreases depending on the amount of load current as illustrated even in an actually set predetermined regulation range and the amount of decrease of the output voltage is increased as the amount of load current increases. Further, the output voltage decreasing region in the drawing is exaggerated for the sake of convenience of explanation.
The reason why such output voltage decreasing is caused is that operation currents of the pair of the differential transistors Q1 and Q2 in the differential amplifier circuit 10 unbalance and an offset of voltage between base and emit of one of the transistors is induced with respect to one of the other transistor. Due to this offset an error is caused for a coincidence detection with the reference voltage Vr.
In order to present such problem, it may be conceived to reduce the open gain of the differential amplifier circuit 10, however, if such measure is taken, a range of the regulation is narrowed. On one hand, in order to reduce unbalance of voltages between base and emitters of the differential transistors it is possible to set the open gain of the differential amplifier circuit 10 to obtain a detection rate of close to 1, however, if such measure is taken, a problem arises that the circuit is likely to oscillate.